1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88128c april 2005 rev. 17 white electronic designs corp. reserves the right to change products or speci? cations without notice. 128kx8 monolithic sram, smd 5962-89598 features access times of 70, 85, 100ns available with single chip selects (edi88128) or dual chip selects (edi88130) 2v data retention (lp versions) cs# and oe# functions for bus control ttl compatible inputs and outputs fully static, no clocks organized as 128kx8 industrial, military and commercial temperature ranges thru-hole and surface mount packages jedec pinout ? 32 pin ceramic dip, 0.6 mils wide (package 9) ? 32 lead ceramic soj (package 140) single +5v (10%) supply operation pin description i/o0-7 data inputs/outputs a0-16 address inputs we# write enable cs1#, cs2 chip selects oe# output enable v cc power (+5v 10%) v ss ground nc not connected block diagram figure 1 C pin configuration the edi88128c is a high speed, high performance, monolithic cmos static ram organized as 128kx8. the device is also available as edi88130c with an additional chip select line (cs2) which will automatically power down the device when proper logic levels are applied. the second chip select line (cs2) can be used to provide system memory security during power down in non-battery backed up systems and simpli? y decoding schemes in memory banking where large multiple pages of memory are required. the edi88128c and the edi88130c have eight bi- directional input-output lines to provide simultaneous access to all bits in a word. an automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. low power versions, edi88128lp and edi88130lp, offer a 2v data retention function for battery back-up opperation. military product is available compliant to appendix a of mil-prf-38535. 32 dip 32 soj * pin 30 is nc for 88128 or cs2 for 88130. top view 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v cc a15 nc/cs2* we# a13 a8 a9 a11 oe# a10 cs1# i/o7 i/o6 i/o5 i/o4 i/o3 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a? i/o? i/o1 i/o2 v ss we# cs1# cs2 oe#
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88128c april 2005 rev. 17 white electronic designs corp. reserves the right to change products or speci? cations without notice. absolute maximum ratings parameter unit voltage on any pin relative to v ss -0.5 to 7.0 v operating temperature t a (ambient) commercial 0 to +70 c industrial -40 to +85 c military -55 to +125 c storage temperature, plastic -65 to +150 c power dissipation 1 w output current 20 ma junction temperature, t j 175 c note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this speci? cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 000v input high voltage v ih 2.2 v cc +0.5 v input low voltage v il -0.3 +0.8 v capacitance t a = +25c parameter symbol condition max unit address lines c i v in = v cc or v ss , f = 1.0mhz 12 pf input/output lines c o v out = v cc or v ss , f = 1.0mhz 14 pf these parameters are sampled, not 100% tested. truth table oe# cs1# cs2# we# mode output power x h x x standby high z icc2, icc3 x x l x standby high z icc2, icc3 x x l x output deselect high z icc1 h l h h output deselect high z icc1 l l h h read data out icc1 x l h l write data in icc1 dc characteristics v cc = 5v, -55c t a +125c parameter symbol conditions min typ max units input leakage current i li v in = 0v to v cc -5 +5 a output leakage current i lo v i/o = 0v to v cc , cs1# v ih and/or cs2# v il -10 +10 a operating power supply current i cc1 we#, cs1# = v il , i i/o = 0ma, min cycle (70-85ns) 120 ma cs2# = v ih (100ns) 110 ma standby (ttl) power supply current i cc2 cs1# v ih and/or cs2# v il , v in v ih or v il 10ma full standby power supply current i cc3 cs1# v cc -0.2v and/or cs2# v cc +0.2v c 1 5 ma v in v cc -0.2v or v in 0.2v lp 1 ma output low voltage v ol i ol = 2.1ma 0.4 v output high voltage v oh i oh = -1.0ma 2.4 v note: dc test conditions : v il = 0.3v, v ih = v cc -0.3v
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88128c april 2005 rev. 17 white electronic designs corp. reserves the right to change products or speci? cations without notice. input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1 ac test conditions ac characteristics C read cycle v cc = 5v, v ss = 0v, -55c t a +125c parameter symbol 70ns 85ns 100ns units jedec alt. min max min max min max read cycle time t avav t rc 70 85 100 ns address access time t avqv t aa 70 85 100 ns chip select access time t elqv t acs 70 85 100 ns t shqv t acs 70 85 100 ns chip select to output in low z (1) t elqx t clz 333ns t shqx t clz 333ns chip disable to output in high z (1) t ehqz t chz 30 30 30 ns t slqz t chz 30 30 30 ns output hold from address change t avqx t oh 333ns output enable to output valid t glqv t oe 25 30 50 ns output enable to output in low z (1) t glqx t olz 000ns output disable to output in high z (1) t ghqz t ohz 030030030ns 1. this parameter is guaranteed by design but not tested. note: for t ehqz , t ghqz and t wlqz , cl = 5pf figure 2 30pf 480? vcc q figure 1 figure 2 255? 5pf 480 ? vcc q 255?
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88128c april 2005 rev. 17 white electronic designs corp. reserves the right to change products or speci? cations without notice. ac characteristics C write cycle v cc = 5v, v ss = 0v, -55c t a +125c parameter symbol 70ns 85ns 100ns units jedec alt. min max min max min max write cycle time t avav t wc 70 85 100 ns chip select to end of write t elwh t eleh t shwh t shsl t cw t cw t cw t cw 60 60 60 60 75 75 75 75 85 85 85 85 ns ns ns ns address setup time t avwl t avel t avsh t as t as t as 0 0 0 0 0 0 0 0 0 ns ns ns address valid to end of write t avwh t aw 60 75 85 ns write pulse width t wlwh t wleh t wlsl t wp t wp t wp 35 35 35 70 70 70 80 80 80 ns ns ns write recovery time t whax t ehax t slax t wr t wr t wr 5 5 5 5 5 5 5 5 5 ns ns ns data hold time t whdx t ehdx t sldx t dh t dh t dh 0 0 0 0 0 0 0 0 0 ns ns ns write to output in high z (1) t wlqz t whz 030035040ns data to write time t dvwh t dveh t dvsl t dw t dw t dw 35 35 35 40 40 40 40 40 40 ns ns ns output active from end of write (1) t whqx t wlz 555ns 1. this parameter is guaranteed by design but not tested.
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88128c april 2005 rev. 17 white electronic designs corp. reserves the right to change products or speci? cations without notice. address data in write cycle 2 - early write, cs 1# controlled t wleh t ehax t eleh t dveh t ehdx t avav data valid we# cs 1# t avel cs 2 address data in write cycle 3 - early write, cs 2 controlled t wlsl t slax t shsl t dvsl t sldx t avav data valid we# cs1# t avsh cs2 figure 2 C timing waveform read cycle figure 4 C write cycle 2 figure 3 C write cycle 1 write cycle 3 address data i/o read cycle 1 (we# high; oe#, cs# low) t avqx t avqv t avav data 2 address 1 address 2 data 1 address data i/o read cycle 2 (we# high) t avqv t elqv t glqv t elqx t shqv t shqx t glqx t avav t ehqz t ghqz oe# cs2 t slqz cs1# address data in write cycle 1 - late write, we# controlled t avwh t elwh t whax t wlwh t dvwh t wlqz t whqx t avwl t whdx t avav data valid high z we# t shwh cs1# data out cs 2
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88128c april 2005 rev. 17 white electronic designs corp. reserves the right to change products or speci? cations without notice. data retention characteristics (edi88128lp & edi88130lp only) -55c t a +125c characteristic low power version only symbol conditions min typ max units data retention voltage v dd v dd = 2.0v 2 C C v data retention quiescent current i ccdr cs1# v dd -0.2v C C 400 a chip disable to data retention time (1) t cdr v in v dd -0.2v 0 C C ns operation recovery time (1) t r or v in 0.2v t avav* CCns note: 1. parameter guaranteed by design, but not tested. * read cycle time figure 5 C data retention C cs1# controlled figure 6 C data retention cs2 controlled data retention, cs 1 # controlled data retention mode t r vcc cs 1 # t cdr cs 1 # v dd -0.2v v dd 4.5v 4.5v data retention, cs 2 controlled data retention mode t r vcc cs 2 t cdr cs 2 0.2v v dd 4.5v 4.5v
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88128c april 2005 rev. 17 white electronic designs corp. reserves the right to change products or speci? cations without notice. package 9: 32 pin sidebrazed ceramic dip (600mils wide) all dimensions are in inches package 140: 32 lead ceramic soj pin 1 indicator 0.020 0.016 0.200 0.125 0.100 typ 15 x 0.100 = 1.500 0.155 0.115 1.616 1.584 0.061 0.017 0.600 nom 0.060 0.040 0.620 0.600 0.050 typ 0.444 0.430 0.840 0.820 0.155 0.106 0.379 0.010 0.006 0.019 0.015 all dimensions are in inches
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs edi88128c april 2005 rev. 17 white electronic designs corp. reserves the right to change products or speci? cations without notice. white electronic designs sram organization, 128kx8 8 130 = dual chip select technology: c = cmos standard power lp = low power access time (ns) package type: c = 32 lead sidebrazed dip, 600 mil (package 9) n = 32 lead ceramic soj (package 140) device grade: b = mil-std-883 compliant m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c ordering information edi 8 8 128 c x x x
|
